FPGA hardware abstraction layer based on high-speed serial bus and implement method thereof

The invention discloses an FPGA hardware abstraction layer based on a high-speed serial bus. With an IP core of the high-speed serial bus provided by an FPGA manufacturer as an external interface, and internal uniform interfaces are provided for users or communication components for use. The FPGA hardware abstraction layer comprises an IRESP module, an IREQ module, a DATA_CTRL module and a TREQ module which all serve as functional modules. The invention further discloses an implement method of the FPGA hardware abstraction layer. Thus, the users or communication components can perform communication in a system through the uniform interfaces provided by the hardware abstraction layer, programs can be freely transplanted between different models and specifications of FPGAs, and the problem that in a software radio system based on the high-speed serial bus, the portability, the operability and the reusability of application software of the FPGAs are poor is solved.