Temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture

A temporal partitioning algorithm for a coarse-grained reconfigurable computing architecture is presented to improve system's performance for satisfying the constraints of application parts executed on the reconfigurable hardware. The input of algorithm is data-flow graph (DFG) created from partitioned source code which will be mapped on the reconfigurable hardware and the reconfigurable hardware description. The critical path and the mobility of each node are obtained by performing the as soon as possible (ASAP) and as late as possible (ALAP) scheduling algorithms. Then the partitioning phase based on the critical path is applied to maximize the operation parallelism and reduce the communication costs by scheduling the node among partitions. Experimental results show the number of partitions is a slight reduction, and the communication cost is dramatically reduced to other temporal partitioning algorithms.