Impact of Charge Trapping and Constant Voltage Stress on Epitaxial p-Ge -on-p- Si and HfO 2 based Al/HfO 2 /p-Ge -on- p-Si/Al structures

The quest for the high speed, low power digital logic circuits urge an imperative demand of compatible high-κ dielectric integration on novel Germanium (Ge) based channel material. Here, first ever a methodical nanoscopic and microscopic probes were attempted to Atomic Layer Deposited, Hafnium Dioxide (HfO2) dielectrics on Molecular Beam Epitaxy (MBE) of p-Ge-on-p-Si stack. Kelvin Probe Force Microscopy based contact potential difference (CPD) analysis reveals that the disintegration of trapped charges lasting for ∼18 hours. The impact of constant voltage stress (CVS) on trapped charges results in variation of threshold voltage (Vth) and hysteresis window (W) were studied. The cyclic Capacitance-Voltage (C-V) characteristics at 0.5 MHz exhibit the shift in the flat band (ΔVfb), ΔVth, and ΔW at 10V stress were ∼0.84V, ∼0.62V, and ∼0.47V, respectively. While the computed interface trap density (Dit) and total effective charge density (Qeff) were ∼8.49 × 1012 eV−1cm−2 and ∼1.81 × 1012 cm−2, respectively. The gate leakage current density, (J) at 5V is 26.53 × 10−6 A/cm2 and reduced by a factor of ∼6.8 after 10V, CVS. Whereas the current density (J) increases from ∼26.53 × 10−6 A/cm2 at 25 °C by a factor of ∼2 at 125 °C. To study the retention and effect of charge trapping, the stress-time analysis was performed for 8000s at 3V (CVS). The r.m.s. surface roughness of HfO2 thin films was found to be ∼0.23 nm. X-ray photoelectron spectroscopy (XPS) depth profiling categorized the elemental composition of thin films. These investigations would help to HfO2/p-Ge-on-p-Si system interfacial engineering well before the Ge based nano device realization.