A Synthesis-based Bandwidth Enhancing Technique for CML Buffers/Amplifiers

A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18 mum CMOS process, and measurements show a BWER of 3.8.