Plans for PANDA Online Computing
2009
The ANDA experiment will not use any hardware trigger, i.e. all raw data are streaming in the data acquisition with a bandwidth of ? 280 GB/s. The ANDA Online System is designed to perform data reduction by a factor of 800 by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays).
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