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A test chip for contact and via failure analysis for 90-nm copper interconnect CMOS technology
A test chip for contact and via failure analysis for 90-nm copper interconnect CMOS technology
2003
Alessandro Cabrini
Paolo Cappelletti
D. Iezzi
Marco Pasotti
Alfonso Maurelli
Guido Torelli
Keywords:
Copper interconnect
Chip
Copper
Electronic engineering
CMOS
Materials science
Optoelectronics
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