FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks

End-to-end packet integrity in TCP/IP is ensured through checksums based on one’s complement addition. Once a negligible part of the overall cost of processing a packet, increasing network speeds have turned checksum computation into a bottleneck. Actually, supporting 100 Gbps bandwidth is a challenge partially due to the difficulties of performing checksums at line rate. As part of a larger effort to implement a 100 Gbps TCP/IP stack on an FPGA based NIC, in this paper we analyse the problem of checksum computation for 100+ Gbps TCP/IP links and describe an open-source solution for the 512-bit wide, 322 MHz buses being used in the 100 Gbps Ethernet interfaces of Xilinx UltraScale devices. The proposed architecture computes thirty-three 16-bit one’s complement additions in only 3.1 ns, more than enough to support 100 Gbps Ethernet links.