A 10-Bit CMOS SAR ADC for Low-Power Sensor Applications

This paper presents design of a low-power 10-bit CMOS successive approximation register analog-to-digital converter chip employing a segmented capacitive digital-to-analog converter. The SAR ADC takes 12 system clocks to finish a conversion cycle and outputs the serial data in the same step. The proposed ADC is designed in a 0.5µm CMOS technology with core area of 0.82mm 2 . It achieves signal-to-noise and distortion ratio of 54.8dB and spurious free dynamic range of 69.9dB at a sampling rate of 40kS/s. The simulated differential non-linearity and INL are −1/2.5 and −1.5/1 LSB. Power consumption is only 432µW when operated at 2.5V supply, resulting in Schreier figure of merit of 134.46dB and 95.9pJ/conv.step.