Automated setup for thermal imaging and electrical degradation study of power DMOS devices

An automated setup for investigation of degradation mechanisms in semiconductor devices under electrostatic discharge (ESD) stress is presented. Vertical-DMOS transistors of a Smart Power technology operating in bipolar snapback mode are studied by combined techniques. The current filamentary behavior imaged by a two-instants transient interferometric mapping (TIM) method and the variation of device DC characteristics are studied as a function of stress current. During repeated stress, a progressive degradation of the DC leakage current at the failure level and a slight gradual change of transfer characteristics are observed. The failure location, resolved in three dimensions by backside infrared microscopy, agrees with the position obtained from the TIM analysis and expected from device physics.