A heterogeneous design methodology for STT-RAM memory system of mobile SoC

Spin-torque transfer random access memory (STT-RAM) has emerged as a potential candidate for universal memory. To exploit its use in System-on-Chip (SoC), this paper proposes a heterogeneous design methodology, which leverages different circuit and structure design techniques to significantly improve the overall efficiency of STT-RAM based memory system, without incurring any extra technology process cost. By using Cacti 6.5 and SimpleScalar simulator, we further demonstrate the performance and efficiency benefit of proposed design methodology in a mobile SoC.