3D High Density: technology, roadmap and applications

After many years of packaging evolution as main industrial driver for 3D integration, even denser integration scheme have gained recently more interest. Slowdown of Moore's law while maintaining the need of high performance and/or low power from one hand, and a combination of performance / form factor from the other, lead research to innovation and alternative solutions. Additionally, difficulty of associating in a same 2D wafer heterogeneous processes (ie: combining Cmos device with “exotic” material, with low temperature dielectric) also gives an opportunity for a high density 3D approach rather than a 2D one. As an example, back-side illuminated imagers (BSI Imagers) players have recently released such 3D density (pitch in the range of 5 to 10 micron) [1] i?½ From now, thinking about a 3D industrial integration within the range of few microns pitch is not anymore a dream. This specific application may raise some interest for other products such as memory denser stacking, partitioning of a large SoC i?½...