A new memory-based FFT processor for VDSL transceivers

This paper presents a new VLSI architecture for fast computation of the N-point discrete Fourier transform (DFT) based on a radix-2 fast algorithm, where N is a power of two. The architecture consists of one complex multiplier, two complex adders, five two-port RAM's, one ROM, and some simple logic circuits. It can evaluate, in average, one DFT sample every (log/sub 2/N)/2 clock cycles. Under 0.35 /spl mu/m CMOS technology, the proposed design is able to operate at a 100 MHz clock rate to compute 22.2M transform samples per second for the case of N=512. The low-complexity and high-throughput feature makes the proposed design attractive for use in high-speed real-time DFT applications, such as the discrete multitone based very-high-rate digital subscriber line transceivers.