Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits

Timing analysis and timing closure are critical steps in digital circuit design. To ensure an error-free design, timing constraints are usually set-based upon the longest path delay from static timing analysis. However, a circuit could have dramatically different internal activity because of the variation of input workload. The path with the longest delay may not be active for certain input workloads, which would enable timing speculation for increased performance. This paper describes an approach to identify the greatest contributors of timing errors and mitigate those errors by replacing certain standard cells in the design. We evaluated our mitigation for several benchmark designs and demonstrated an error-free performance gain up to 37%. The entire design flow uses Synopsys electronic design automation tools and customized scripts, which can be adapted for other designs.