Smart Switching Network based Asynchronous Binary Search ADC

This paper presents a binary search analog to digital converter based on sub-ADC scheme in which the 16-bit architecture is split into four stages and the whole architecture uses only N comparators instead of (2N-1) comparators. The proposed design enables comparators in sequential manner using asynchronous logic and achieves low power and less chip area with high conversion speed. The proposed binary search ADC has been implemented in 180 nm CMOS process and consumes 8mW of power when operated at 1.8 V. The transient result verifies that the proposed design achieves the conversion rate of 87.26 MSPS and its spectrum specifies the ENOB, SNDR and SFDR as 11.3 bit, 23 dB and 25 dBc respectively with 0.158pJ/conv-step of Walden figure of merit (FOM w ) at sampling frequency of 20MSPS.