A Proposal for Synthesis of Synchronous Counters

Advancement in technology and increased complexity of circuits had created more challenges for testing the functionality and errors in the circuit. Increased power requirements during test mode are one of the major challenges faced. This paper presents an efficient study on the synthesis of digital circuits by combining both Mentor Graphics HDL Design and Xilinx VIVADO FPGA flow. The experiment is done by using the circuit of a synchronous up counter. Power and area requirements are analyzed and compared with the corresponding gate-level models for various bit lengths of the counter circuit.