A high-throughput clock-less architecture for soft-output Viterbi detection

Viterbi detectors are widely used in data recording channels in the timing loop as well as in the digital back end before error-correction decoding to detect data in the presence of inter-symbol interference (ISI) and noise. Further, soft reliability values assist in the decoding of outer codes. The state-of-the-art implementations of the Viterbi algorithm are synchronous which consider the ‘worst-case’ propagation delays of the combinational blocks for the purpose of timing analysis. This can be avoided by using asynchronous circuits that offer ‘average case’ latencies without a clock distribution network which is one of the most power-consuming units in the existing integrated circuits. In this paper, we present a high-throughput clock-less architecture for a soft-output Viterbi detector. In 180-nm technology node, we obtain a 66.7% reduction in the power consumption for our asynchronous design in comparison to a synchronous version of the detector with throughput requirements of the order of 1.5 Gb/s. Simulation results in 65-nm technology results in 44.2% reduction in power consumption sustaining a throughput of 2.4 Gb/s.