Design and implementation of a dependable CPSoC for automotive applications

Safety-critical cyber-physical systems-on-chip, consisting of analog/mixed-signal front- and back-ends combined with massive digital many-processor cores, are being increasingly applied. The imminent collision detection chip for cars is an example of this and such a complex system requires zero downtime and a very high dependability. By on-line monitoring the health status of processor cores and IPs and taking counteractions, we have accomplished this goal via IJTAG-compatible embedded instruments and appropriate embedded software. An IJTAG-compatible Iddt monitor has been designed, a slack-delay embedded instrument for detecting timing issues, as well as a monitor for detecting intermitted resistive faults in interconnections. By the on-chip replacement of degraded (non-healthy) cores, the lifetime can be increased by a factor of around four of our mixed-signal cyber-physical systems-on-chip.