Hardware architecture of MAP algorithm for turbo codes implemented in a FPGA

Turbo codes represent a very powerful channel coding technique for the next generation of mobile communications. The research is focused on the development and implementation of turbo coding-decoding algorithms in high-speed programmable platforms (DSP and FPGA) for a better performance in terms of error correction, power consumption and speed. The MAP (maximum a-posteriori probability) algorithm represents the best performance choice for turbo decoding block. The main objective of implementation is to design structures for turbo decoding near to the theoretical performance using sub-optimal architectures. In this work we present a hardware implementation of the log-domain version of the AMP algorithm (log-AMP). This version of the algorithm gives an excellent approach to the Shannon limits and allows the description of simple blocks based on arithmetic operators, like the MAX* operator.