Gate-tunable graphene-organic interface barrier for vertical transistor and logic inverter

One of the key requirements for efficient organic-electronic devices is the creation of a negligible energy barrier for carrier injection at the metal-organic interface. Here, a graphene-organic interface with an almost negligible energy barrier is demonstrated in a high-performance hybrid heterojunction device. The gate-tunable current-voltage characteristics show that the electronic transport can be tuned from an interface-limited to a bulk-dominated regime by lowering the graphene-organic interface energy barrier. N-type transistors with a PTCDI-C8 organic thin film as an active layer provide an ON-OFF current ratio of ∼107, while similar p-type transistors with a CuPc molecular layer reach an ON-OFF current ratio of ∼105. Furthermore, logic inverters with standby current as low as ∼1 pA are demonstrated using a combination of both n- and p-type transistors.