The development of iHARP: a multiple instruction issue processor chip

The objective of the HARP project is to design, build and test a processor which executes non-numeric benchmarks at a sustained execution rate in excess of two instructions per cycle. Earlier work at Hatfield centered around the design of an abstract HARP architectural model. This paper describes iHARP, a physical realisation of the HARP architectural model within the constraints of a single VLSI chip.