Learning-Based DRM and Energy Optimization for Manycore Dark Silicon Processors

For the last several decades, technology scaling has led to the continuous integration of devices, and microprocessors will have more cores integrated in the future. However, due to the failure of Dennard’s scaling (Dennard et al. IEEE J Solid-State Circuits 9:256–268, 1974), chip power density is increasing on technology nodes since transistor and voltage scaling is no longer linear. The consequence is the emergence of the so-called dark silicon manycore microprocessors , which mean only a percentage of cores can be powered on the chip due to the power and temperature limitations. Recently, architecture researchers predicted that future manycore (100–1000 cores) silicon dies can only be powered up partially (the so-called dark silicon) as power constraints will not allow all the cores to be active at the same time. Such manycore systems pose new challenges and opportunities for power/thermal and reliability management of those chips (Esmaeilzadeh et al., Proceedings of the 38th Annual International Symposium on Computer Architecture, ACM, New York, 2011).