Development of a small die-small form factor flip chip package for application in LAN products

LAN products using Flip Chip interconnect necessitated the development of a new packaging technology involving very small die sizes and package form factors. This paper describes the development of the package assembly technology, the challenges associated with it, the thermalmechanical aspects of the package, application to a Dual Port Gigabit Ethernet Controller (on 90 nm Si process), and finally the future direction of these packages. The small die and package sizes used in the mixed signal process technology was a major departure from the traditional larger size FCBGA packages from assembly and design perspectives. Small die handling and issues surrounding saw and singulation of the wafers posed several challenges that needed to be solved. The chip attach process was also problematic due to the small size of the package and die. The assembly of the die on the package as well as the test/BI related design rules had to be aggressively pursued in order to accommodate the die on the package with relatively small areas available for packages as small as 15 mm. The handling media for such small FC packages differed from the traditional FCBGA was also part of the development. By using Flip Chip technology and replacing the inductive bond wires used on previous generation Gigabit product packages, it enabled the high speed interconnect PCI-Express to be added to the product and provide ‘benchmark’ performance. The substrate technology used was essentially the same as traditional FCBGA, but the size and layer restrictions prompted some co-design requirements on the die bump pattern. The objective was to enable a low-cost and hence lowest possible size and lowest possible layer count package. The thermo-mechanical enabling for the products using these SFF packages was challenging due to the space constraints and customer application requirements. A separate heat sink was not desirable for the thermal solutions. The bare die packages were characterized for thermal solutions which showed the limits of the package to meet certain product thermal requirements. The substrate technology had limited thermal capability, and certain enhancements in it for better thermal dissipation was outside the purview of the technology envelope. The product at hand ultimately had to settle for a heat sink to meet thermal needs. The mechanical characterizations were done for both solder joints integrity fatigue and shock with successful results for 1.0 mm ball pitch.