An Optimized Design Strategy for the Hardware Implementation of the Hearing Aid Algorithms

In this paper, a new design strategy for the hardware implementation of hearing aid algorithms is proposed. Two familiar hearing aid algorithms—Wide Dynamic Range Compression (WDRC) and Automatic Gain Control (AGC)—are implemented in one circuit as an example. By putting the common arithmetic procedures into common module, the operation units can be used repeatedly. In this way, the area and power consumption are visibly reduced.