Design and performance of a low-noise, low-power consumption CMOS charge amplifier for capacitive detectors

In this paper, a new design of low noise, low-power consumption charge amplifier is described. Theoretical results show that a total output noise voltage reduction of 0.261 mV has been obtained. This value corresponds to a 46% reduction compared to the noise performance of a conventional charge amplifier. A complete readout system including the proposed charge amplifier has been realized in a 0.8-/spl mu/m semiconductor on insulator (SOI) bipolar complementary metal-oxide-semiconductor (BiCMOS) process. A measured noise performance of 450 electrons at 0 pF with a slope of 44 electrons/pF for a shaping time of 45 ns, a conversion gain of 20 mV/fC and 1-mW power consumption have been obtained.