Fermi level pinning engineering by Al compositional modulation and doped partial silicide for HfAlO/sub x/(N) CMOSFETs

Threshold voltage (V/sub th/) tuning by controlling Fermi-level pinning (FLP) position on HfAlO/sub x/(N) high-k dielectrics is demonstrated for CMOSFETs. Two kinds of methods for the effective work function tuning have been proposed. One is to control the Al concentration ([Al]) in the top interface of HfAlO/sub x/(N) to modulate the FLP position. The other is the doping into the PtSi/sub x<1.0/ (partial silicide: PASI) gates on HfAlO/sub x/(N) dielectrics. Symmetrical V/sub th/ values are obtained for the cases of poly-Si gate and FUSI (foil silicide)-NiSi gate n- and p-MOSFETs when the Al concentration is controlled in HfAlO/sub x/(N).