Ultra-thin buried nitride integration for multi-V T , low-variability and power management in planar FDSOI CMOSFETs

We highlight an original solution to adjust the threshold voltage (V T ) of Fully Depleted Silicon-On-Insulator CMOS down to L=20nm gate length thanks to charge storage in a thin buried nitride layer. In particular, high performance pMOS with I off =500nA/µm (V T =−0.2V) are demonstrated in a gate first approach. This technique is combined with back-bias for power management and with a smart process compensation technique to improve the device variability down to σ VT =4mV for L=30nm and W=500nm.