Impact of high-k gate dielectric with different angles of coverage on the electrical characteristics of gate-all-around field effect transistor: A simulation study

Abstract In this paper, we consider the electrical performance of a circular cross section gate all around-field effect transistor (GAA-FET) in which gate dielectric coverage with high-k dielectric (HfO2) over the channel region has been varied. Our simulations show the fact that as high-k dielectric coverage over the channel increases, ION/IOFF ratio and transconductance over drain current (gm/ID) will be enhanced. Moreover, we investigate the impact of channel length scaling on these devices. The obtained results show that subthreshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage (VTH) roll-off will be reduced as a result of scaling. In this work TCAD simulator was concisely calibrated against experimental data of a GAA-FET from IBM. The Schrodinger equation is solved in the transverse direction and quantum mechanical confinement effects are taken into account.