A CMOS image sensor with a simple fixed-pattern-noise-reduction technology and a hole accumulation diode

A simple fixed-pattern-noise (FPN)-reduction technology, which consists of a five-transistor pixel circuit, a hole accumulation diode for sensing elements, and a correlated-double-sampling (CDS) circuit with an I-V converter in an output stage circuit, is applied to a 1/3-inch 640/spl times/480-pixel CMOS image sensor. The five-transistor pixel circuit outputs the current mode pixel signal with a reset level and a signal level successively in one pixel period. The I-V converter is designed to reduce a signal-line voltage to close to the ground level in order to give sufficient voltage to an amplification transistor in a pixel. The CDS circuit receives a pixel signal from the I-V converter and performs as an FPN-reduction circuit by subtracting a signal level from a reset level of a pixel signal. Owing to the technology, the CMOS image sensor achieved a sensitivity of 0.52 V/lx/spl middot/s, a saturation signal of 200 mV, a dynamic range of 61 dB and a dark current of 150 pA/cm/sup 2/.