PLL frequency synthesizer based on all-digital dynamic acceleration locking technology

The invention relates to a PLL frequency synthesizer based on an all-digital dynamic acceleration locking technology. The PLL frequency synthesizer comprises a phase frequency detector, a current coded control, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider, a programmable timing module, a digital automatic control, a loop parameter control and a configurable register, wherein the four modules, the programmable timing module, the digital automatic control, the current coded control and the loop parameter control, form a phase-locked loop dynamic acceleration locking controller. The invention has advantages of all-digital implementation, simple control scheme, small circuit scale and low power dissipation. A control module has a rapid and automatic reset function. The influence on a loop is little. The PLL frequency synthesizer is very suitable for the field of wireless communication or frequency hopping communication with high integration level, low power dissipation and rapid locking performance.