A 64-by-64 pixel-ADC matrix

An 8-bit 5-MS/s Wilkinson-type analog-to-digital converter (ADC) cell has been designed for parallel in-pixel digitization in a 64-by-64 pixel readout ASIC. Due to its simplicity, low power consumption, and small area requirement this type of ADC is suitable for pixel-level implementations. 720-ps time stamps are generated globally by means of 8-bit Gray-code counters. They are distributed column-wise to the pixel blocks together with a conversion-start signal along 13-mm long transmission lines. The analog input voltage is sampled-and-held on a capacitor. A pixel-internal current source is used to generate a voltage ramp. The conversion into a digital word is done when the ramp voltage equals the reference voltage, and the corresponding time stamp is latched. The ASIC is fabricated in IBM's 130-nm CMOS technology. The pixel-wise gain trimming properties provide a homogeneous gain distribution. Full matrix measurements demonstrate the achievement of a signal-to-noise ratio of 70 dB when all 4096 ADCs are working simultaneously. 75 % of the pixels show DNL better than 0.4 LSB, and the INL remains within ± 0.5 LSB for 99% of the pixels. The area and power dissipation of the in-pixel ADC amounts to 100 × 120 μm 2 and 150 μW at 1.2-V power supply, respectively.