Test Strategies for Gated Clock Designs

One of the ways often used to design for low-power consumption during functional operation in CMOS devices is to gate off clocks to areas of logic not needed for the current state of operation. By gating off clocks to state elements that are known to not need updating, the dynamic switching current can be reduced compared with allowing state elements to update when you don’t care what they contain. When clocks are gated, some amount of DFT is necessary to ensure ATPG can be used to create meaningful tests. This chapter describes some of the DFT approaches that can be applied so ATPG can deal with gated clocks. In addition, this chapter explores ways in which functional clock gating may be exploited to help reduce power during test.