A BiCMOS programmable frequency divider

A BiCMOS programmable frequency divider which is a major functional block of a frequency synthesis IC based on a phased-locked loop is described. Innovative techniques are demonstrated to solve many incompatibility problems between ECL and CMOS techniques. It is shown that a similar concept can be applied to other high-speed designs. The frequency divider has 15 stages and operates at 165 MHz. It occupies 0.375 mm/sup 2/ of die area, which is only a third of what is required in an all-bipolar version. Power consumption is about 55 mW, which is 80% of that of the all-bipolar version. >