Memory-Aware Loop Paralleling for Coarse-Grained Reconfigurable Architectures

The parallelization of sequential programs and the optimization of critical loops are challenging issues in the time of multi-core architectures. Coarse-Grained Reconfigurable Architecture (CGRA) is introduced to accelerate these data-intensive applications, while the access delay introduced by the massive memory accesses contained in those loops has become the bottleneck of CGRA's performance. In this paper we focus on the parallel optimization of critical loops under the CGRA's hardware constraints. At first we propose a novel approach to parallelize loops by multi-level tilling. Then a genetic algorithm is introduced to schedule tiled loops with memory-aware object functions. Data locality and communication cost are optimized during the parallel processing as well. Experimental results show that our approach can generate more effective parallel tasks to improve the data locality and load-balanced execution, while obtains better speedup compared with the memory-unaware parallel processing.