Voltage solution in PFET areas

A method of manufacturing a semiconductor device includes providing a structure of a voltage-rich silicon on insulator (SSOI) structure, the SSOI structure has a on a substrate (10) arranged dielectric layer (20), a on the dielectric layer (20) arranged in the silicon-germanium layer (30) and one directly on the silicon-germanium layer (30) arranged layer (40) of a voltage-rich semiconductor material, comprising forming a plurality of ribs (43, 45) on the SSOI structure, forming a gate structure (50) over a portion of at least one rib in an nFET region away, forming a gate structure (60) over a portion of at least one rib in a pFET region of time, a remove a gate structure (60) over the portion of the at least one rib in the pFET region of time, removing the silicon-germanium layer (30), which has been exposed by the removal, as well as Forming a new gate structure (90) over the portion of the at least one rib in the pFET region of time, so that the new gate structure (90) surrounds the portion on all four sides.