SOI design for a high-performance IO interface

SOI technology is well suited for high speed digital circuits. However, its history effect due to the floating body poses a major challenge to analog circuits. This paper presents the design of a high-performance IO interface (FlexIO TM [5]) used in Cell Broadband Engine TM processors [1][4], currently in mass production. The design has been scaled across 90nm, 65nm, and 45nm SOI CMOS processes. The parallel interface implemented in 45nm SOI comprises 5 transmit and 5 receive bytes with each link unidirectionally running at 6.4Gb/s achieving BER ≪ 10 -20 . The paper discusses clocking, IO, and ESD aspects of the design in SOI processes.