Sparse LU Solver FPGA

OLUTION ain decomposition adopted in several ulation [2]. These ut not in values of solvers performed nce, however, was mplementations on the 20% mark he irregularity of asons for the poor ources of sparse the nature of the by most multicore ic dataflow which hardware resources s. In this paper we A implementation ers. A parallel LU latency of both cations. The low ree major design ed floating point a customized data to eliminate times were essential to resources.