Frequency synthesis with arbitrary input clock rate and rational K/L multiplier ratio

The architecture of a frequency synthesizer that generates an arbitrary-frequency output clock from an arbitrary-frequency input clock is presented. This design supports fully-programmable synthesis ratios, including integer-N, fractional-N and rational-K/L ratios. An earlier solution presented by the authors requires an input clock frequency above a few hundred mega-hertz for a low phase noise output clock. In the present work, a digital noise-canceling technique is introduced to eliminate the noise contribution from the input frequency divider, thus allowing an input clock rate reduction down to tens of mega-hertz.