Low-Voltage Scaled 6T FinFET SRAM Cells

Planar bulk devices suffer from high random dopant fluctuations (RDF) when scaled down to sub-32 nm technology nodes. This is considered as a major roadblock for the integration of these devices in high density 6T SRAM cells [1, 2]. The increasing variation of transistor parameters like VT, ION, IOFF, etc., can result in a large variability in performance and power. The possibility of leaving the channels undoped and their excellent immunity against Short Channel Effects (SCE) favors the use of FinFET-based multi-gate devices [3] for these technology nodes.