Investigation of Temperature Dependence, Device Scalability, and Modeling of Semifloating-Gate Transistor Memory Cell

A semifloating-gate transistor had been proposed and its memory function has been demonstrated recently. In this paper, we further investigate its temperature dependency, device scalability, and device modeling. The high-temperature behavior is studied by measuring its endurance, retention, and disturbance immunity at 85 °C. The device scalability down to the 14-nm technology node is investigated by simulation. Its macrodevice model for circuit design is also developed. Finally, a memory array with the specific peripheral circuits is designed using the device model developed in this paper.