A CMOS cyclic folding A/D converter with a new compact layout technique

In this paper, a 9-bit 2MS/s CMOS cyclic folding A/D Converter(ADC) for a Battery Management System(BMS) is described. The scheme of the ADC is based on a cyclic style to reduce chip area and power consumption. To obtain a high speed ADC performance, further, we use a folding-interpolation architecture. The prototype ADC is implemented with a 0.35μm 2P4M n-well CMOS process. The measured results for INL and DNL are within ±1.5/±1.0 LSB. The ADC demonstrates a maximum SNDR and SFDR of 48dB and 60dB, respectively, and the power consumption is about 1mW at 3.3V. The occupied active die area is 10mm 2 .