Implementing the Blue Midnight Wish Hash Function on Xilinx Virtex-5 FPGA Platform

This paper presents the design and analysis of an area efficient implementation of the SHA-3 candidate Blue Midnight Wish (BMW-256) hash function with digest size of 256 bits on an FPGA platform. Our architecture is based on a 32 bit data-path. The core functionality with finalization implementation without padding stage of BMW on Xilinx Virtex-5 FPGA requires 84 slices and two blocks of memory: one memory block to store the intermediate values and hash constants and the other memory block to store the instruction controls. The proposed implementation achieves a throughput of 56 Mpbs.