AnOptimization ofBusInterconnects Pitch for Low-power andReliable BusEncoding Scheme

32-bit BUS Abstract- Energy consumption isone ofthemostcritical constraints inthecurrent VLSIsystem designs. Inaddition, fault tolerance ofVLSIsystems isalso oneofthemostimportant re- Processor L ECC/ ECGCLow (SimpleSalar Power EDC EDC Power M m (ipScar Encoder!Encoder! Encoder!Encoder!/ em quirements inthecurrentshrunkVLSI technologies. Thispaper Architecture)Decoder Decoder Decoder Decoder presents lowpowerandfault tolerant busencoding methods considering coupling effects ofbusinterconnects. Experiments using SPEC2000benchmark programs showthattheproposed Aredundant bitExtra code bitAredundant bit methodscaneffectively reducesignal transitions withfault tolerance. Moreover, theresults showthattheoptimization ofbus Fig1 Thearchitecture whichexploits thecombination ofECC.EDC code interconnects pitch canincrease theeffectiveness oftheencodingandlowpower code method. I.INTRODUCTION