Design of a Page Replacement Policy for Hybrid PCM and DRAM Memory

Phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy. However, PCM has two critical weaknesses compared to DRAM. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 8 times slower than that of DRAM. To cope with this situation, this paper presents a new memory management scheme that uses a small amount of DRAM together with PCM to absorb most memory writes into DRAM. To do this, we analyze the characteristics of memory write references and present a new page replacement scheme that significantly reduces the number of write operations that occur on PCM and also reduces power consumption.