Hardware implementation of non-binary turbo code for DVB/RCS

Double binary convolutional turbo codes, using Circular Recursive Systematic Convolutional (CRSC) codes as component codes, have been shown to outperform binary turbo codes. These codes are adopted in the Digital Video Broadcasting--Return Channel via Satellite (DVB-RCS) standard. The outstanding coding performance of these codes intrigues the investigation of hardware implementation issues. In this thesis, first a simplified Max_Log_MAP algorithm is derived for the Non-binary convolutional turbo code, and then different aspects of the implementation issues of the decoder with VLSI are explored. In addition, a complete decoder VLSI design of non-binary convolutional turbo code for DVB/RCS will be presented. After discussing several quantization and normalization schemes, a new optimal renormalization approach will be proposed. With this new approach, the decoder can be speeded up considerably. In order to save area, a practical simplification method of branch metric calculation is introduced, which makes the whole design much more efficient. From an architectural point of view, an optimal full pipelined structure is designed with the forward path metric and backward path metric recursive circuits being optimized for speed and other functions including concise interleaver generation, data input, branch metric calculation being optimized for area. In the last part of this thesis, another pipelined area saving method is proposed. The design is modeled in Very high speed integrated circuit Hardware Description Language (VHDL) and synthesized on a single chip FPGA (Xilinx Virtex-E). According to the RTL level and gate level simulation results and the in-chip test result, the decoder can work up to 7 Mbits/s data rate at 6 iterations with VirtexE FPGA.