Multi-Step Verification Environment for a Chip Design using SoC platform

This paper presented an efficient verification stra tegy for the platform based design. A goal of the verification task is to detect all design faults an d provide with full verification coverage at the ea rlier design. The proposed verification strategy employed iterative v erification stages. For a case study, this strategy was used in a verification of a modem chip design complying with IEEE 802.11a standard. It was successfully verified the entire design functionality and its interface with 100% co verage in shorter design cycles. Keyword : SoC (system on chip), verification, platform-bas ed SoC.