Investigation on the ESD failure mechanism of integrated circuits in a 0.11µm CMOS process

The ESD failure mechanism of integrated circuits in a 0.11µm CMOS process was investigated experimentally in detail. The leakage current was presented through I–V measurements, some hotspots were observed on the failed chips when ESD occurring. The study suggested two failure modes in the experiments. One was defined as thermal ESD failure, and the large current between one pad and another pad can be regarded as the key precondition for the occurrence of thermal ESD failure. The other failure mode was electric ESD failure. The defect-current was the main factor for such failure, and occurred mainly in device layer.