A compact four quadrant CMOS analog multiplier

Abstract The design of a very compact four quadrant CMOS analog multiplier is presented. The circuit has a very simple design, consisting of only four transistors and ten resistors, enabling a very small silicon area consumption. Furthermore, the multiplier can work in both subthreshold and saturation region, allowing it to operate over a wide range of frequencies. Subthreshold biasing sets the multiplier into a low-frequency low-power mode, while saturation biasing sets the multiplier to a high-frequency high-power mode. These two modes can be implemented for a very low voltage power supply. Finally, the proposed multiplier uses a minimum amount of nodes, allowing it to operate at high frequencies. Simulations show a maximum operating frequency of 300 kHz @ C L = 30 pF , a THD of ≈1% for an input sine wave of 100 mV and DC = 800 mV, and a minimum power supply of ( V DD - V SS ) ≈ 0.5 V when operating in the sub threshold region. In order to validate theory and simulations, a prototype of the proposed multiplier was fabricated using ON SEMI 0.5  μ m technology, showing its feasibility.