Bracing technology in a contact plane of semiconductor devices using strained conductive layers and an insulating spacer

In complex semiconductor devices are strain-inducing material having a reduced insulation resistance, or with a certain conductivity, such as metal nitrides, and the like used in the contact level, in order to improve the performance of circuit elements, such field effect transistors. For this purpose a verformungsinduzierendes material is efficiently trapped on the basis of a dielectric layer stack, which is patterned prior to the application of the actual interlayer dielectric material, wherein side wall surface areas are masked on the basis of spacer elements.