NBTI degradation: From transistor to SRAM arrays

A novel composite model had been recently introduced to physically explain the mean pMOS threshold voltage shift (V TP ) induced by NBTI degradation at transistor level in a quantitative way. This model is here extended to include the statistical variations introduced by intrinsic fluctuations. In a second time, the model is extrapolated up to SRAM arrays by analyzing the SRAM bitcell sensitivity to transistor degradation. This approach allows quantitative prediction of NBTI-induced V MIN variations and access time T aa degradation during burn-in operations. The key findings include (a) demonstration of non-normality of V TP shift distribution (b) NBTI contribution to product V MIN drift arises from both mean V TP drift but also from increased V TP dispersion, and (c) V TP shift non-normality is smoothed out at product level by time-zero variation of the six transistors of the SRAM bitcell.