A high-speed parallel sensing architecture for multi-megabit flash E/sup 2/PROMs

A high-speed parallel sensing architecture for high-density 5-V-only flash E/sup 2/PROMs is described. A source-biasing technique enhanced the cell current while minimizing the read disturbance problem. Flip-flop-type differential sense amplifiers are arranged between every two pairs of bit lines, so that half the memory cells on the same work line are sensed simultaneously. Self-time dynamic sensing was developed for high speed and stable sensing and also decreased read disturbance and operating current. Simulated results show that a sub-10- mu A cell current is successfully sensed in 40 ns. In the program mode, the differential amplifier acts as a column latch, which substantially reduces the chip size. >